1. Field of the Invention
This invention relates to integrated circuit devices and more particularly to techniques and structures for forming integrated circuit devices intended for low voltage operation but which are able to switch substantially higher voltages and which are fabricated utilizing standard processes.
2. Description of the Prior Art
Integrated circuit devices are well known in the prior art. A cross-sectional view of a P channel device is shown in FIG. 1a. P channel device 10 is formed in N- substrate 16 and includes P+ type source 11 and P+ type drain 12. Formed above and between source 11 and drain 12 is gate oxide 13 and thereupon is formed gate 14. N+ type contact 15 is formed to allow electrical connection to substrate 16. A schematic diagram of the structure of FIG. 1a when utilized as an open drain output buffer is shown in FIG. 1b. Substrate 16 is connected to source 11 which in turn is connected to a source of positive voltage V, thereby preventing the PN junctions formed between the source and the substrate, and between the drain and the substrate from becoming forward biased. Drain 12 serves as the output terminal of the device. Gate 14 receives an input signal which controls the operation of transistor 10, thus determining the output voltage available on terminal 12. With a logical 0 signal (typically 0 volts) applied to gate 14, P channel transistor 10 turns on, thus connecting the positive voltage V to output terminal 12. Conversely, a logical 1 signal (typically V) applied to gate 14 causes transistor 10 to turn off, thus not supplying a voltage to terminal 12.
With transistor 10 turned off (i.e., a logical 1 applied to gate 14) and drain 12 connected through an external load device (not shown) to ground, a depletion region 17 forms surrounding drain 12 (FIG. 1a) in which the free charge carriers are depleted. In other words, electrons are forced away from drain 12 due to its relatively low voltage with respect to substrate 16 which, as previously described, is connected to V. However, near gate 14, which is connected to positive voltage V, electrons are attracted, thereby reducing the width of the depletion region to width d as shown on FIG. 1a. Thus, for an increasing voltage differential between drain 12 and substrate 16, and thus a descreasing distance d, the electric field between drain 12 and substrate 16 increases. For a sufficiently high electric field between drain 12 and substrate 16, the PN junction formed between drain 12 and substrate 16 (substrate 16 is also referred to as the bulk silicon with respect to P channel transistor 10) breaks down under reverse-bias, and current flows from substrate 16 (connected to V) to drain 12 (connected to ground through the external load device, not shown). This phenomenon is hereinafter referred to as the drain to bulk reverse-bias breakdown.
Another type of output buffer is shown in the schematic diagram of FIG. 2a. The complementary metal oxide silicon (CMOS) Push-Pull output buffer 20 includes P channel MOS transistor 17 having its source connected to a positive voltage supply (V), its drain connected in common with the drain of N channel MOS transistor 27, and its gate 14 connected to input terminal 39. Similarly, the gate of N channel transistor 27 is connected to input terminal 39, and the source 23 of N channel transistor 27 is connected to ground. Output terminal 38 is provided between the drain 12 and drain 22 of MOS transistors 17 and 23, respectively. With a logical 0 signal (typically 0 volts) applied to input terminal 39, P channel transistor 17 turns on and N channel transistor 27 turns off, thus providing a voltage substantially equal to V on output terminal 38. Conversely, with a logical 1 signal (typically 5 volts) applied to input terminal 39, P channel transistor 17 turns off and N channel transistor 27 turns on, thus effectively grounding output terminal 38 through transistor 27. Thus output buffer 20 can, alternatively, source current to output terminal 38 from voltage source V, or sink current from output terminal 38 to ground. Hence, output buffer is referred to as a CMOS push-pull output buffer.
A cross-sectional view of one structure which provides the circuit of FIG. 2a is shown in FIG. 2b. As previously described, the drain to bulk reverse-bias breakdown voltage of P channel transistor 17 prevents the switching of high voltages. A similar problem with the drain 22 to P well 40 (P well 40 serves as the bulk silicon for N channel transistor 27) reverse-bias breakdown voltage is present in N channel transistor 27. In typical prior art CMOS logic devices utilizing push-pull output buffers, the reverse-bias breakdown voltage between P well 40 and drain 24 is approximately 15 volts. Thus, referring again to FIG. 2a, with a voltage in excess of the drain to bulk reverse-bias breakdown voltage applied as the positive supply voltage V, P channel transistor 17 will conduct current from substrate 16 (connected to V) to drain 12 when transistor 17 is turned off, thus providing an undesirable high voltage on output terminal 38. Similarly, with a high voltage in excess of the drain to bulk reverse-bias breakdown voltage applied to output terminal 38 (i.e. through a conducting transistor 17), transistor 27 will conduct current from drain 22 to P well 40 (connected to ground) when turned off, thus providing an undesirable current path between output terminal 38 and ground. Thus, the undesirable drain to bulk reverse-bias breakdown of transistors 17 and 40 provides incorrect voltage levels on output terminal 38, high power dissipation, and often results in irreversable damage to transistors 17 and 40, thus destroying the integrated circuit device.
One prior art technique for eliminating the problem of reverse-bias bulk to drain breakdown when switching high voltages is to develop a more complex fabrication process which increases the bulk to drain reverse-bias breakdown voltage. Such special processing techniques are described, for example, by Heisig in an article entitled "BIMOS--A New Way to Simplify High Power Custom Interface", Proceedings of 1981 CICC, pp. 8-12; Yamaguchi et al., "Process and Device Design of a 1000 Volt MOS IC,", IEDM Technical Digest, 1981, pp. 255-258; and Buhler et al., "Integrated High-Voltage/Low Voltage MOS Devices", IEDM Technical Digest, 1981, pp. 259-262, each of which is hereby incorporated by reference.
Another attempt to minimize the effect of the undesirable bulk to drain reverse-bias breakdown voltage is described by Yoshida, et al, in U.S. Pat. No. 4,317,055, issued Feb. 23, 1982, and which is hereby incorporated by reference. As shown in their FIG. 13, for example, Yoshida et al utilize a plurality of MOS transistors Q1 through Qn, each of which has a relatively low drain to bulk reverse-bias breakdown voltage. This plurality of MOS transistors are connected having their drains and sources connected in series with the source of Q1 connected to ground, and the drain of Qn connected to the output terminal (D). A first resistive voltage divider is formed by resistors R(N+1) through R2n between a positive bias voltage VB and ground, with each node of the first resistive voltage divider being connected through one of a plurality of diodes d.sub.1 through d(n-1) to the gates of all transistors with the exception of Q1. The gate of transistor Q1 receives the control signal which controls the state (on or off) of transistor Q1. The Yoshida, et al structure also utilizes a second resistive voltage divider formed by resistors R1 through Rn, which is connected between the output terminal (D) and ground. Each node of this second resistive voltage divider is connected to the control gate of an associated transistor, with the exception of transistor Q1. This second resistive voltage divider is used to increase the gate voltages on transistors Q2 through Qn when the voltage applied to the output terminal (D) by external devices (not shown) exceeds the bias voltage VB. Diodes d.sub.1 through d(n-1) are required to prevent this high external voltage from being applied to other devices (not shown) within the integrated circuit device.
Of importance, the Yoshida et al structure requires a substantial amount of components in addition to transistors Q1 through Qn in that Yoshida et al require two separate voltage dividers and a plurality of diodes for each output terminal of their integrated circuit device. Furthermore, because one of the resistive ladder dividers of each of Yoshida's output buffers is connected between the output terminal (D) and ground, the Yoshida, et al structure provides a finite DC impedance to the external circuitry (not shown) connected to the output terminal D when the output stage is turned off. Often this is not acceptable. Thirdly, Yoshida, et al structure is an open drain output buffer and thus does not provide an output terminal which is capable of both sinking current or, alternatively, sourcing current.